The present invention relates to a PLL (Phase Locked Loop) circuit, in particular, a PLL circuit using, as a VCO (Voltage Controlled Oscillator), a ring oscillator which can select the number of stages in delay circuits connected in multistage fashion. The PLL circuit is used for various LSI (Large Scale Integration) circuits.
FIG. 5 is a block diagram showing a basic structure of a PLL circuit.
In this PLL circuit, reference numeral 51 denotes a phase comparator, 52 denotes a charge pump circuit, 53 denotes an LPF (Low Pass Filter), 54 denotes a VCO, and 55 denotes a frequency divider.
FIG. 6 is a block diagram showing an example of the frequency divider 55 in FIG. 5.
The frequency divider comprises a plurality of stages of flip-flop(F/F) circuits 61.
FIG. 7 is a block diagram showing an example of the VCO 54 in FIG. 5.
The VCO comprises a frequency-variable type ring oscillator in which an odd number of stages of voltage-variable type inverter delay circuits IV (7 stages in this example) are connected in a loop.
In the conventional PLL circuit using the ring oscillator having the above structure as the VCO 54, a frequency of an output from the ring oscillator 54 is divided by a number M by the frequency divider 55, the frequency-division output and a reference signal are compared by the phase comparator 51, a control voltage in association with the comparison output is generated by the charge pump circuit 52 and the LPF 53 and supplied to the VCO 54 as a delay time control input of the inverter delay circuits IV of the VCO 54.
Thereby, loop control is performed so that a phase of the frequency-division output is controlled to be the same as that of the reference signal IN. In the state where loop control is stabilized (a phase-lock state), the VCO 54 enters the state of oscillation at a frequency obtained by dividing the frequency of the reference signal IN by the number M. Further, an output signal (a PLL output) of the VCO 54 is supplied to various circuits as a system clock signal, for example.
When the PLL circuit enters the phase-locked state as described above, a stable state continues unless a phase difference is generated between the frequency-division output and the reference signal IN. A frequency range in which the PLL circuit can retain the phase-locked state is called a lock range. This lock range differs according to the number of stages of the inverter delay circuits IV.
FIG. 8 shows an example of the relationship between the cases where the number of the stages of the inverter delay circuits IV in the ring oscillator shown in FIG. 7 is 5, 7 and 9, and lock ranges A, B and C of the PLL output frequency (a system clock frequency) is changed.
Specifically, in accordance with the number of the stages of the inverter delay circuits IV, the delay time of the whole delay circuits greatly varies in a step-like fashion. The delay time of the whole delay circuits varies almost continuously in a certain range by varying the delay time of each inverter delay circuit IV (the varying amount is small) in the state of fixing the number of stages of the inverter delay circuits IV.
Therefore, according to the PLL circuit having the above structure, the oscillating frequency of the VCO 54 is substantially determined in accordance with the number of the stages of the inverter delay circuits IV, and enters the phase-locked state by control of the amount of delay time of the inverter delay circuits IV.
In the meantime, in the PLL circuit using the conventional ring oscillator as the VCO, as shown in FIG. 8, one ends of the adjacent lock ranges overlap each other if the number of the stages of the inverter delay circuits IV is changed. For example, one end of the lock range B of the ring oscillator having 7 stages of delay circuits IV overlaps with one end of the lock range A of the ring oscillator having 5 stages, and one end of the lock range B of the ring oscillator having 7 stages of the delay circuits IV overlaps with one end of the lock range C of the ring oscillator having 9 stages.
In the conventional art, when the number of stages of the inverter delay circuits IV is once determined in accordance with the PLL output frequency based on designed product specifications, the lock range (frequency band width) depending on the number of the stages is fixedly determined.
Further, there are cases where the PLL circuit enters the locked state in the vicinity of the boundary of the fixedly determined lock ranges. In the vicinity of the boundary of the lock ranges (for example, a frequency at the vicinity of the boundary of the lock ranges B and C is indicated by F1), the PLL output frequency goes out of the lock range in its number of the stages due to the manufacturing dispersion of elements and environmental conditions, etc. Therefore, there are cases where stability of the PLL operation is not ensured and the system clock signal cannot be stably supplied.
Furthermore, though the lock range determined by the number of stages of the delay circuits IV of the ring oscillator may be extended, in this method the extensible range is limited, and stability of the PLL operation is not still ensured in the vicinity of the boundary of the extended lock ranges, where jitter (fluctuation of edge of the output signal) of the PLL output frequency occurs and the PLL property deteriorates.
Moreover, in the conventional PLL circuit, whenever the PLL output frequency is greatly changed in accordance with the product specifications, it is necessary to redesign the mask pattern for changing the number of the stages of the delay circuits IV of the ring oscillator so as to obtain a desired lock range, which causes increase of manufacturing cost due to extension of a period of design and causes an obstacle to prompt commercialization of the PLL circuit.
As described above, the ring oscillator used as the VCO in the conventional PLL circuit has a problem that the stability of the PLL operation is not ensured and a system clock signal cannot be stably supplied in the case of the PLL circuit enters a locked state in the vicinity of the boundary of the lock ranges which are fixedly determined.
Further, whenever the PLL output frequency is greatly changed in accordance with the product specifications, it is necessary to redesign the mask pattern to change the number of the stages of the delay circuits IV of the ring oscillator so as to obtain a desired lock range, which causes increase of manufacturing cost due to extension of a period of design and causes an obstacle to prompt commercialization of the PLL circuit.
The present invention has been made in order to solve the above problems. The object of the present invention is to provide a PLL circuit in which stability of the PLL operation can be ensured by selecting a lock range in which a designated PLL output frequency is included in a central region thereof, by switching the number of stages of the delay circuits of the ring oscillator. The switching of the number of stages of the delay circuits can be easily switched so that a desired lock range can be obtained even when the PLL output frequency is greatly changed, thereby un-necessitating redesign in the number of stages of the delay circuits, inhibiting increase of manufacturing cost, and enabling prompt commercialization of the circuit.